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C9530-404 - IBM Integration Bus V9.0 Solution Development - Dump Information

Vendor : IBM
Exam Code : C9530-404
Exam Name : IBM Integration Bus V9.0 Solution Development
Questions and Answers : 48 Q & A
Updated On : December 14, 2018
PDF Download Mirror : C9530-404 Brain Dump
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C9530-404 IBM Integration Bus V9.0 Solution Development

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C9530-404 exam Dumps Source : IBM Integration Bus V9.0 Solution Development

Test Code : C9530-404
Test Name : IBM Integration Bus V9.0 Solution Development
Vendor Name : IBM
Q&A : 48 Real Questions

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IBM IBM Integration Bus V9.0

Arguments Between AI Is a good component | killexams.com Real Questions and Pass4sure dumps

americans (or computers) who enter into an argument will also be thought of as adversaries. And most of us have heard about adversarial AI methods. however arguments will not have to be fight, an argument does not have to be structured to outcomes in a winner and a loser. Many human arguments are in fact greater like belief sharing.

And when there are more than two contributors, the interplay becomes a sturdy and legitimate studying experience for the entire contributors. When the dialogue strikes to a topic that a participant does not have skills (or holds a false perception), it gives the chance to accumulate that skills from the different participant(s). The misalignment of reported beliefs at the very least indicators the need for extra research on that problem.

within the case of people, this is the factor at which each person reaches for his or her smartphones. When there are three or more participants and nearly all of them agree on a common perception then it appears pragmatic to at the least trust that almost all position is extra proper. [Note: This never works with politics or religion in my experience.]

k, earlier than I collapse a philosophical mumbo-jumbo rabbit hole let's shift our context to the world of engineering, computers, and AI.

right through the heritage of technology, people have been delegating movements to instruments. and not incredibly, our considerations about the correctness of those movements correlates directly with the magnitude of the consequences of those actions. elementary issues just like the lowly force cooker have advanced to have assorted failsafe mechanisms to offer protection to us from having a very dangerous kitchen day. If anyone of those mechanisms "decides" that the force is too high then it reduces the pressure. one other very simplistic mechanical conversation is the aircraft fashion protection switch regularly used to enable and disable the aircraft autopilot.

I fantasize a conversation something like this:human: (accidentally bumps autopilot on-off swap)change: did you actually want to turn it off?human: yesswitch: ok, elevate up the cover and move my togglehuman: thanks

Image title

but of path, because the complexity of the conduct of the instruments increases and if the repercussions of a foul decision develop into lifestyles-threatening we are able to now not manipulate that conduct in such an easy binary assemble. a very good instance of a gadget involving magnificent complexity blended with extremely excessive stakes is the space shuttle.

Image title

When it changed into designed the area shuttle turned into probably the one most advanced vehicle ever created. It wrangled more power and had extra components than any automobile earlier than. It required operational functional manage with millisecond precision. It also posed a enormous possibility to the crew, the launch site, and any person or thing that might have been inside range of an errant flight direction. in view that premise, a great deal of robustness became engineered into the launch and navigation programs. a big part of the robustness became offered via having numerous flight computers working in parallel. 

definitely, the house shuttle was designed to have five similar computer systems, which all worked on the launch administration assignment in parallel. together, they compared the high-degree output commands (engine throttling and gimballing, flight handle surfaces, and many others.) to determine that they agreed within some predetermined volume of suitable error.

It operated whatever like this: Three of the computer outputs were compared consistently and severely and if one of those computer systems mentioned a outcome drastically distinctive from the other two inconsistent desktop could be instantly swapped out for the fourth computing device which changed into computing in parallel however in the past become not submitting any command "votes". If the new quorum of three computer systems agreed satisfactorily then every little thing went alongside just great and the flight continued invariably. If after the laptop swap a disagreement was nevertheless detected then the computer with essentially the most divergent reply was overlooked.

The fashioned application design was speculated to encompass all 5 computers in a greater complicated fallback scheme but by the point of genuine gadget development and application integration, it become determined that the "three+1" pooled computing device gadget become more convenient to enhance and verify. Simulation recommended that it would fail simplest three times in the 1 million. And when regarded against the bigger chance of all of the other systems on the shuttle it turned into decided that this failure rate become sufficient.

notice: The fifth desktop become kept on board as a hardware backup on the grounds that it was tougher to engineer it out of the shuttle then to just go away it in! in spite of the fact that the algorithmic decision-making of the area shuttle control computers become some distance less complicated and mysterious as our AI-driven autonomous vehicle techniques are nowadays the redundancy changed into viewed as essential to the success of the area shuttle.

This brings us to the catch 22 situation we have today with AI-based mostly self-riding automobiles. information stories pop up constantly about an self reliant car doing the incorrect thing. The AI might suppose a light blue coloured truck is only the sky and pressure through it. It may absolutely misunderstand whether a pedestrian is crossing the street or now not. It may misinterpret marks on the pavement to be site visitors governing strains and do inappropriate things (Google "witches entice independent automobile").  considering the fact that just about all of these AI-based using brains are in response to neural nets they endure from two problems:

  • They simplest study what they've experienced (again and again) in their practising information

  • they are "black packing containers" and can't clarify why they did what they did

  • Image title

    [Note: This doesn't even begin to address other moral and ethical issues such as the classic trolley problem. These are difficult issues no matter how simple Isaac Asimov made it seem with his "Three Laws of Robotics". ]

    One good component in regards to the state of self sustaining motors today is that there are lots of americans working independently on the identical difficulty. The total field of self sufficient motors obtained a jumpstart from DARPA Grand problem in 2004. the hassle began primarily in universities followed by using R&D agencies with deep pockets (e.g. Google). Then it stepped forward to auto businesses and eventually transportation corporations (e.g. Uber). There are dozens of in a position agencies working on practically exactly the same problem: Safely drive automobiles via cities, on highways, out and in of parking amenities, and many others. every one of these impartial programs ingests huge amounts of sensor information and reduces it to a couple pretty fundamental outputs:

  • Go ahead (or reverse)

  • Set speed to X kph

  • turn Y levels to the left (or appropriate)

  • Brake at Z percent

  • No depend how differently each of those impartial techniques analyzes and methods its sensory input, the outputs are few and intensely simple. The outputs of anybody of the programs can without difficulty be in comparison to the outputs of another device. can you see where here is going?

    or not it's time to delivery an argument — smartly, at the least a strong debate — between these diverse self reliant systems. here's a idea test i want you to agree with:

    think about a analysis vehicle with diverse (possibly even dozens) of independently developed AI drivers operating in parallel. All of their simple driving command outputs will also be compared in parallel. an awful lot just like the area shuttle flight manage desktop system these outputs may also be in comparison for consistency. however we will use this tips to glean a good deal more than a simple contract. The tightness (ordinary deviation) of the outputs provides a demonstration of how well a selected riding circumstance is known. remember all of those AI drivers are diverse. They were raised through distinct researchers (parents). They skilled different practicing statistics (lived distinct lives). They each and every have a distinct viewpoint on the project. 

    What I believe is most fascinating during this scenario is that a automobile pushed with the aid of a committee of AI drivers could definitely train itself the way to pressure more suitable. An AI driver that advised an motion that the group considered inappropriate would be able to remember that condition as well as what it's going to have done. It may confidently add verified training information to its personal own collection. After snoozing on this statistics (back in its personal very own server farm) it should be able to do stronger with this selected circumstance in the future. instances the place many of the handle outputs are an awful lot much less constant would generate a request to the researchers (parents) for extra training information examples (experiences) like this condition (the AI could show their folks the video of the complicated circumstance). These new practicing examples could be shared with the community as a whole.

    I feel this method has loads of technological merit. despite the fact, politically, I do predict some proprietary sharing considerations between these a variety of independent businesses related to competitiveness. but I predict that the autonomous driving labs will realize that if one self reliant motor vehicle drives over a child buggy or avoids a stray cat only to crash into a crowded bus cease then all the self sustaining using organizations will suffer the unhealthy publicity. the earlier all AI systems will also be depended on as secure on the road the sooner they may be able to sell giant numbers of them. And after all, they are handiest sharing the knowledge of their consequences, now not their exact proprietary expertise.

    At this aspect some of you're pondering here's only a crackpot theory from some wild-eyed futurist (a.k.a. yours truly the author). however analysis efforts are being made during this direction. initial work is being performed the use of this approach these days to realize viable AI using blunders and alert the human.

    Image title

    one of the vital things that the MIT AVT look at is getting to know is this form of argumentation between competing AI. under is a brief video about what they are doing:

    the total analysis paper may also be discovered right here.

    I consider this approach is awfully pleasing for self sufficient vehicles, and i are expecting to look it applied extra broadly in the future. It certainly may well be utilized to robotics in regular, and there are many ways i can imagine it becoming in with medical and even financial functions. preserve a watch on this expertise. 

    ingesting AI in byte sized functions is the top of the line strategy to transform digitally. #BuiltOnAI, EdgeVerve’s enterprise software, offers you with every thing you need to plug & play AI into your business.  study greater.

    subject matters:

    artifical intelligence ,adversarial desktop researching ,machine studying algorithms ,three laws of robotics


    professionals and Cons of IBM Blueworks — with an IBM Blueworks alternative | killexams.com Real Questions and Pass4sure dumps

    here's concerning the strengths and weaknesses of IBM Blueworks BPM along with a doable choice for Blueworks (Tallyfy). a whole lot of it's borrowed from Gartner, with some portions edited and cleaned up.

    Please notice this disclaimer. I’m affiliated with Tallyfy — a workflow and BPM platform which differentiates through remarkable ease-of-use, client-dealing with features and suppleness to power adoption in contemporary teams.

    IBM is improving the intelligence of its Smarter manner items by utilizing complementary Watson technologies, resulting in what it calls Cognitive company Operations. It additionally better cloud-based mostly deployments by way of enhancements in Blueworks live and a licensing approach that enables customers to observe buy credits to both on-premises or cloud models of BPM. This overview centers on IBM business technique manager v.eight.5.6, IBM enterprise process supervisor on Cloud, Blueworks live, Operational choice manager (ODM) superior v.8.7 and enterprise display screen v.8.5.6. iBPMS initiatives additionally may also consist of IBM Analytical resolution administration, IBM Bluemix, IBM Streams, IBM FileNet content supervisor, IBM Integration Bus, IBM MobileFirst Platform and other products.

    Strengths of IBM Blueworks and IBM BPM
  • IBM offers a notably large set of product facets, able to imparting just about any characteristic favored to address the eight dimensions of the Gartner technique IQ Framework. Its products assist most vital industry requirements, so builders can conveniently combine and match IBM items with application from different vendors.
  • IBM is a leader in decision management and analytics, together with rule processing in IBM BPM and ODM, BAM in IBM BPM and business video display, CEP in IBM ODM advanced and IBM Streams, and superior analysis in Watson Analytics and Watson cognitive services.
  • IBM has made it simpler for company people to participate in development through enhancements in Blueworks are living and a new essential manner Accelerator procedure design tool. IBM business procedure supervisor also helps business clients execute unfamiliar or advanced tasks at runtime the use of its common system train UIs.
  • Weaknesses of IBM Blueworks and IBM BPM
  • IBM BPM-primarily based methods can also be challenging to design, configure and installation because most advanced applications require combining distinct items and environment many parameters and alternate options. IBM items overlap each other in content administration, company rule processing, BAM, CEP, portal, workflow/orchestration, alerting and different capabilities.
  • customer references surveyed via Gartner provided lukewarm comments on usual delight relative to any other iBPMS vendors.
  • consumers report that IBM company manner manager requires a comparatively excessive stage of expertise, a controversy chiefly in small projects the usage of the on-premises IBM products. although, individuals with advantage in the product appear to be extra attainable than in past years.
  • choice to Blueworks BPM — Tallyfy problem — historic BPM makes modelling advanced

    a pretty good alternative to Blueworks stands out as the potential to mannequin procedures conveniently. simply because you have some big BPMN model doesn’t make you suave or constructive. in the end, people can/will nonetheless have to really do the technique, which comes down to electronic mail/spreadsheets (except you desire a 6-month IT venture). It’s with ease ridiculous to make use of BPMN in today’s age — the place people collaborate and don’t comply with flowcharts anyway. Any choice to Blueworks must absolutely eliminate using flowcharts and in selected — BPMN. in contrast to what you’ve heard about BPMN — it’s now not a “standard” in any respect — as each seller creates their personal taste of it. This makes the a whole lot-touted “typical” and “portability” element of it next to unimaginable to obtain.

    Tallyfy uses simple lists that nonetheless have the entire elements of flowcharts difficulty — just IT and manner analysts map methods. Managers crave true vigour to map a manner themselves

    Tallyfy is the handiest tool that allows collaboration amongst any kind of function/grownup — for the reason that most americans consider the simplicity of the tool in 60 seconds. The choice to Blueworks isn't in fact an choice at all — it’s an inevitable swap.

    Tallyfy allows for any individual to collaborate on documenting a system issue — nobody appears at process maps. You need your procedures to be in primary, executable list structure

    This skill you want workflow application like Tallyfy that in fact offers that simplicity, along with the vigor you need.

    Please — let’s drop flowcharts and BPMN — it’s absolutely broken and lifelessaccept as true with an exquisite alternative to IBM Blueworks — Tallyfy

    It integrates to everything, and it truly works for everyone.

    Take a look at a video demo of Tallyfy below, as a workable, person-friendly choice to Blueworks.


    appropriate 10 most reliable BPM software products | killexams.com Real Questions and Pass4sure dumps

    Posted December 13, 2016 via Drew Robb     remarks

    These are among the many optimum company technique management software options obtainable.

    simply how massive is the business procedure administration (BPM) application market? It is dependent upon who you ask. foreign data Corp. (IDC) has pointed out the BPM market is experiencing a growth cost of eight.2 % per 12 months and is value more than $3.2 billion yearly. customer marketing Insights observed the full become extra like $3.four billion and would be rising to $10 billion by 2020. however an additional analyze from MarketsandMarkets places the value significantly bigger at $6.96 billion through the end of this yr and rising to $13.52 billion through 2021. That’s an annual boom rate of 14.2 percent.

    A fresh Forrester analysis survey discovered, youngsters, that handiest 26 percent % of corporations use BPM or workflow techniques to support nearly all of their enterprise approaches. And sixty nine p.c suppose that these techniques will help most or all of their firm’s tactics inside the subsequent two years. So there's a variety of room for boom, which might possibly be why so many firms are concerned during this field.

    "BPM software is a crowded market with many providers becoming smartly and capable of invest in innovation,” talked about Maureen Fleming, an analyst at IDC.

    however that are the most reliable BPM utility items to consider? here are some candidates:

    Bpm’online has out-of-the-box procedures for provider, sales and advertising and marketing that sit on a company system administration platform. The device permits for modeling and working complicated approaches, even if they are branched or parallel approaches. The business stresses an open configuration, agile deployment options and straightforward customization.

    The core of the platform is its BPM engine, which provides tools for design, execution, monitoring and evaluation. It supports runtime process evolution — modification of working approaches. It additionally makes use of the company manner model and Notation (BPMN) average, probably the most established enterprise manner notation on the planet. in consequence, manner diagrams are effortless to remember and easy to tailor to specific organizational wants.

    “BPM allows organizations to notice inefficiencies and painlessly modify approaches, besides assisting replicate successes all the way through the company,” talked about Katherine Kostereva, CEO and managing partner at bpm’on-line. “if you evaluate why some teams are attaining their goals whereas others are struggling, you should be in a position to determine methods that foster success. BPM software also permits a company to: establish what is at the moment happening, how predictably and why; to measure how efficiently the procedure is working; to gather assistance in an effort to take into account the place waste and inefficiency exist and their usual influence on quite a lot of facets of the enterprise; and to advance new superior methods to address quite a lot of concerns.”

    BP Logix manner Director is a BPM platform developed on .internet technology that is internet-primarily based, cellular-competent and browser-agnostic. It coves workflow automation, wise types and the capacity to reuse business suggestions devoid of programming. It has a simple interface for the introduction of advanced workflows and it builds electronic types using Microsoft observe.

    utility AG’s Digital enterprise Platform (DBP) is asserted to enable corporations to transition easily to a more consumer-responsive, aggressive and agile business. the usage of the DBP Agile manner Platform, agencies can create enterprise functions in response to orchestrated, managed and monitored enterprise strategies or workflows. it's also loaded with BPM surest practices and content to get users begun and to aid them directly reveal results.

    “We see the BPMS market transitioning from ordinary method management to an engagement trend adaptive purposes attitude,” referred to Rick McEachern, vice president product advertising and marketing, agile method platform, utility AG. “this type of shift makes it possible for them be more conscious of client necessities, regulatory adjustments and their competitors.”

    He introduced that in addition to BPM method orchestration, clients are looking to see how their systems are operating right now — now not simply after the fact. For that they want real-time monitoring and analytics capabilities to assist them obtain enterprise transparency with the aid of discovering techniques and performing analytics according to information, methods and organizational metrics. application AG’s DBP platform is integrated with these capabilities.

    AgilePoint NX is a Microsoft-primarily based platform with accessories referred to as Server, clothier, Portal, types and reports. These operate collectively to kind an utility construction framework that makes it possible for company and IT to collaborate on BPM and different functions. it is obtainable on premises and within the cloud.

    The Oracle BPM Suite 12c platform offers a single design-time and unified engine for tactics, instances, rules, human initiatives, types, analytics and integration. it's built-in with Oracle WebCenter content and Oracle WebCenter Portal.

    The suite gives support for collaboratio, and is declared to enrich technique effectivity via elevating utilization and throughput. Visibility into strategies is more desirable with the aid of offering true-time analytics. furthermore, it is asserted to simplify compliance.

    The company additionally offers the Oracle process Cloud carrier, which is declared to empower the business person to manipulate the lifecycle of company approaches and gain actionable perception on system health and SLAs, all in the cloud.

    The Pega 7 platform includes BPM, case administration, utility building, a call hub, mobile functionality and cloud functions. It is declared to make it easy to construct enterprise applications that fit organizational procedures.

    Appian includes tools for rapid constructing of BPMN-based techniques, a local method repository to catch and outlets method models for reuse, business rules to outline guidelines and procedures, a forms interface for creation of assignment types and dashboards, and complicated experience processing for tracking, inspecting and responding to business activities.

    Tibco is well widespread in the container of utility integration. It brings this be aware of-the way to the BPM field and is experiencing boom in its BPM offerings. even though it become acquired in 4Q14 through Vista fairness partners, it continues to operate and expand.

    Its business manner platform is composed of TIBCO ActiveMatrix BPM + TIBCO Nimbus. This gives a three-pronged attack into the BPM container with equipment for business manner analysis and BPM analytics that sit down on an common enterprise procedure platform.

    Summarizing IBM’s BPM portfolio isn’t handy. Its items consist of IBM business technique supervisor, Blueworks live, Operational decision manager, company display screen, IBM Analytical choice administration, IBM Bluemix, IBM InfoSphere Streams, IBM FileNet content manager, IBM Integration Bus and IBM MobileFirst Platform.

    “IBM is incessantly increasing past its natural systematic, on-premises method to BPM in order to handle cloud-based mostly deployment and greater agile, light-weight initiatives,” talked about Gartner analyst Rob Dunie.

    AuraPortal Helium is Microsoft .internet-primarily based BPM platform that's strongest in Latin the us, the center East and Europe. Its implementation in the Costa Rican countrywide insurance Institute has 2 million lively users.

    while these tools and suites are advantageous in providing the technological foundation for a BPM initiative, this is still a difficult box. There isn't any one-size-matches-all answer to which product could be the most useful fit. these engaged in product alternative, for this reason, should understand that product evaluation is just part of the picture — but one which can set the organization on the path to BPM success.

    “Managing enterprise procedures without problems is a tricky problem for ultra-modern business leaders, as a result of lots of the techniques that are used within tactics are rigid and complex to exchange swiftly,” mentioned Dunie. “it is much more important today for techniques to be bendy and responsive, permitting process participants to intelligently respond to pursuits.”

    Drew Robb is a contract creator focusing on know-how and engineering. at present dwelling in Florida, he's originally from Scotland, the place he acquired a degree in geology and geography from the school of Strathclyde. he's the creator of Server Disk administration in a windows atmosphere (CRC Press).


    C9530-404 IBM Integration Bus V9.0 Solution Development

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    IBM Integration Bus V9.0 Solution Development

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    Power savings of embedded computing modules (ECMs) over FR-4 implementations | killexams.com real questions and Pass4sure dumps

    Embedded computing modules (ECMs), which employ silicon circuit board (SiCB) technology, are beginning to compete with FR-4 as the solution of choice in many design cases. The reasons for this include improved packing density, improved speed, and reduced power. This paper addresses some of the improvements in power consumption available to users of ECMs.

    December 31, 2009 – SiCB technology allows bare die FPGAs, CPUs, and memory to be placed together on a single silicon substrate. The SiCB can also include various associated support parts such as oscillators, bypass caps, calibration resistors, etc. Once the components are merged together on the silicon substrate, the SiCB is typically attached to a rugged substrate (e.g. ceramic or FR-4) using BGA technology. The result is an ECM that can be placed on the customer’s FR-4 board, again using BGA technology.

    The power savings within an ECM come from a reduction in I/O power. In a typical system as described below, an immediate reduction of 7.4W, or 22% in overall power, can be achieved on an ECM as compared with an equivalent FR-4 based system. There are two primary sources for this reduction: (1) Reduced I/O parasitics due to the use of bare die and closer distances between die, and (2) Elimination of termination resistors or on-die termination due to the improved I/O parasitics and the lossy characteristics of SiCB wiring.

    This paper will explain how reduced I/O parasitics and removal of termination resistors can lead to power reductions of 22% in a typical system. These results can be easily adapted to other system configurations to find the power reduction potential in a variety of systems. As ECMs become more popular, additional savings can be achieved through optimization of the FPGA I/O cells for the SiCB environment.

    Example system configuration

    A typical system that can take advantage of SiCB technology is shown in Figure 1 below. This system consists of an FPGA with 8 channels of DDR3 SDRAM memory. Each memory channel consists of 2 1Gb ×16 DDR3 SDRAMs with shared command/address bus and a ×32 data channel. The DDR3 interface operates at 533MHz (1066 Mbps). For the SiCB-based implementation, all of the memory interface signals are able to be contained within the ECM. Only FPGA I/Os that are used for other purposes are required to be delivered out of the ECM.

    Figure 1: Typical system implemented on conventional FR-4 and new SiCB technology.

    A key component of finding the power savings is to determine the number of I/Os required for implementing the 8 channel DDR3 memory system. Each channel consists of a single DDR3 clock and command/address bus. For DDR3, there are 2 clocks (CK/CK#) and 22 command/address signals (13 address, 3 bank address, 3 command, 1 chip select, 1 clock enable, and 1 odt control pin). The data interface for a single channel consists of 4 bytes of data. Each byte consists of 8 data signals, 2 data strobe signals (differential, bi-directional), and 1 data mask for a total of 11 data signals per byte. Therefore, the full channel consists of 4×11=44 data signals. Note that for a Read operation, the data mask is not used, so the full data channel for a Read consists of 4×10=40 data signals.

    Table 1 summarizes the number of I/Os related to the memory interface:

    Table 1: Number of DDR3 memory interface signals.

    Power savings through signal wiring parasitics

    It is visually apparent from Figure 1 that the overall dimensions and the interconnect lengths between FPGA and memory are significantly reduced for the SiCB-based implementation. In addition, the removal of the FPGA and memory packages removes significant package parasitics from the signal path. These reductions contribute to reduced power through reduced parasitic capacitance, while providing a cleaner signaling environment as well.

    Signal trace parasitics

    For the FR-4 implementation, the signal routing length is estimated to be around 58mm based on recent siXis designs. This includes about 45mm of 50Ω trace routing and about 13mm of routing within the FPGA and memory packages. The 45mm trace is assumed to be a typical microstrip construction with 170μm width, 17 μm thickness, and 100μm dielectric thickness. The relative permittivity of the dielectric is assumed to be 4.5. With these parameters, the capacitance and inductance of the 45mm line are about 5.4pF and 13.7nH, respectively.

    For the SiCB-based implementation, the signal routing length is reduced by about 60%, from 58mm to about 23mm worse case. For the silicon process, the 23mm length corresponds to a capacitance of about 3.7pF, an inductance of about 8.4nH, and a resistance of about 23Ω at DDR3 frequencies. Higher ratios of resistance to inductance are also possible, depending on the particular requirements of the signaling channel. Thus, the signal channel behaves like a lossy transmission line where reflections are significantly dampened by the resistance of the line.

    Package parasitics

    The packaged FPGA and DRAM contain additional capacitance and inductance that can be eliminated when moving from an FR-4 implementation to an SiCB-based implementation. The removal of the package inductance improves signaling, while the removal of the capacitance reduces the power required to switch the signals. Packaged and bare die parasitic capacitance for the DDR3 memory and FPGA have been estimated based on a review of IBIS models from various suppliers. For the DDR3 memory, the review showed that the ratio of die and package capacitance to total capacitance was consistent among various memory vendors. Based on this conclusion, the die capacitance for the DRAM is estimated as a percentage of the common datasheet values. The package parasitics of the FPGA were estimated using the Altera Stratix family of FPGAs, including IBIS models for the Stratix III and datasheets for both the Stratix III and Stratix IV. The Stratix IV datasheet lists an input capacitance of 8pF. Using the breakdown of package vs. die capacitance from the IBIS model, an estimate for the Stratix IV package and die capacitance was obtained. The results for packaged and bare die DDR3 and FPGA capacitance are shown in Table 2 below. The C_Total value represents the total capacitance for the packaged FPGA or memory. The C_Die value is the left over capacitance applicable when using bare die. For reference, the average package inductance is shown as well. The FPGA and DRAM inductance for an SiCB-based implementation is reduced to zero.

    Table 2: Typical FPGA and DDR3 memory die and package parasitics.

    Power savings due to reduced parasitics

    The power savings due to reduced signal capacitance can now be calculated using the estimated signal capacitance for FR-4 and SiCB-based implementations and the number of signals required to support the memory interface. This estimation is done using a standard formula for the power required by a toggling signal to charge its capacitance.

    where: n = number of signals switching T = Average toggle rate; number of low to high transitions per clock cycle C = Total capacitance of the signal f = Clock frequency (T*f = frequency of the toggling signal) V = Voltage swing of the toggling signal

    Table 3 shows the tabulation of each term and the final power consumed by the memory interface for both FR-4 and SiCB-based implementations. Note that the voltage swing has been derived from the termination settings, which are detailed in the next section. Due to the lossy nature of the SiCB signal channel, the voltage swing is similar and taken to be the same for both implementations.

    The following switching assumptions are used for the switching power calculation:

  • Memory interface is running continuous read/write operations with interleaved banks
  • Clocks run full-time (100% toggle rate)
  • New command/address presented at each clock cycle (50% toggle rate)
  • Data toggles at the maximum rate (100% of clock toggle rate for DDR)
  • Access is equally split between Read and Write operations (50% toggle rate each)
  • Table 3: Power consumption due to signal capacitance. [1] The ODT pin is unused in the SiCB-based implementation because the on-die termination is disabled.

    Power savings through termination resistors

    As discussed above, the signal channel on an SiCB tends to be lossy compared to a typical FR-4 implementation. For the signal distances used on SiCBs, this lossy nature can be turned into an advantage because the signals are inherently damped and do not require termination resistors to provide excellent signal quality. Because SiCB wires are much shorter than FR-4 wires, the reduced signal propagation speed due to R*C delay is more than compensated for by the shorter length.

    This section will analyze the power consumed by a typical FR-4 termination scheme for DDR3 as shown in Figure 2. This scheme is consistent with recommendations of FPGA vendors when using discrete DDR3 components. Once the power required for the FR-4 termination scheme is calculated, this power can be translated into savings for the SiCB-based implementation, which requires no termination.

    Figure 2: Typical DDR3 termination scheme for FR-4 implementation.

    The power required for the termination scheme can be estimated by simply looking at the DC current consumed when the signal is driven to a high or a low state. The power related to charging the capacitance of the signal line has already been considered in the previous section.

    To analyze the power for driving a high or low in each termination case, one needs to solve the simple resistance network associated with each termination type. Since the FR-4 implementation uses nearly lossless transmission lines, the transmission line can be considered as a short circuit for the DC analysis. For each analysis, the output driver input is shorted to 0V or VDD and the resulting output voltage (VOUT) and the DC power can be calculated. These results are shown in Table 4 below as PFPGA(High/Low) and PMEM(High/Low). Note that the power has been calculated separately for the FPGA and the memory. This was done to identify which portions of the termination current flow from the FPGA power supply and which portions flow from the memory power supply. To find the total power delivered from the FPGA and the memory, the single signal results are scaled according to the number of signals, the percentage of time that the signal drives high/low, and the percentage of time that the data is driven for Write vs. Read commands. This final calculation is summarized by the following equations.

    where: DT = Percentage of time that the signal is driven (not tri-stated) Total signals = Total number of signals of the particular type HT = Percentage of time that the signal is driven high; (1-HT) = Percentage of low time PFPGA(High/Low) = DC power consumed by the FPGA for terminating a single high/low signal PMEM(High/Low) = DC power consumed by the memory for terminating a single high/low signal

    Table 4: Output voltage and DC power dissipation for typical DDR3 termination scheme. [2] For the termination analysis, the differential clock is treated as one pair rather than two independent signals.

    Summary of FR-4 vs. ECM power dissipation

    Typical FPGA and memory core power

    Having calculated the I/O power dissipation for switching the signal line and for termination, the final step before identifying the power savings is to estimate the core power required for the DDR3 memory and for the FPGA. The ×16 DDR3 SDRAM is assumed to operate at 533MHz (1066Mbps), which corresponds to a speed bin of DDR3-1066. The operating mode is assumed to be continuous interleaved burst mode (IDD7). A review of various memory vendors showed that the current specifications vary considerably from about 200mA to about 380mA. Therefore, the average of four leading memory vendors was taken, which corresponds to about 265mA per device. At 1.5V, this represents about 400mW per device or about 6.4W for the full memory system.

    The core power for the FPGA is estimated based on a heavily utilized Altera Stratix IV configuration. The estimates were obtained from the power calculation software provided by Altera. Note that this calculation did not include termination power or power required to switch the output signals. These components of the power consumption have been calculated in previous sections. Table 5 shows the breakdown of the Core power for the FPGA.

    Table 5: FPGA core power for a typical configuration.

    Total power consumption and savings through SiCB technology

    With all power contributions now accounted for, the total power consumption for the typical system can be summarized as shown in Table 6 below. As the results show, a typical system such as the one used for this analysis can benefit from a power savings of 7.4W when using embedded computing modules (ECMs) containing SiCB technology. For the example FPGA configuration, which represents a heavily utilized Stratix IV, this translates to a reduction in power of 22%. For systems with lower FPGA resource utilization and therefore less overall power consumption, the relative savings offered by SiCB technology would of course increase. Additionally, as ECMs become more popular, additional savings can be achieved through optimization of the FPGA I/O cells for the SiCB environment.

    Table 6: Power dissipation for FR-4 vs. ECM implementation of example system.

    Biography

    David Blaker is VP of engineering and manufacturing at siXis Inc., 3021 E. Cornwallis Road, Research Triangle Park, NC USA; 919-248-9193, e-mail: dblaker@sixisinc.com.

    References

    (1) IBIS models and datasheets from various 1Gb ×16 DDR3 SDRAM memory vendors: [a] Micron: MT41J64M16LA; [b] Samsung: K4B1G1646E; [c] Hynix: H5TQ1G63AFP; [d] Elpida: EDJ1116BBSE

    (2) IBIS models and datasheets from FPGA vendors: [a] Altera Stratix III (datasheet and IBIS model); [b] Altera Stratix IV (datasheet only, IBIS model not available)

    (3) Altera AN-520-1.1, "DDR3 SDRAM Interface Termination and Layout Guidelines," May 2009.

    (4) Altera PowerPlay Early Power Estimator (v9.0.1 B4)



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